Accurately measuring a component’s Failures In Time (FIT) is the key to keep designs as simple as they should be, and avoiding over-design and schedule risks.

Avidan Efody, Verification Architect at Mentor Graphics, presented on the fault de-rating techniques available at various abstraction levels, and explained how they should all be combined to get a realistic estimate of FIT(Failures in Time) numbers and ISO 26262 architectural metrics at the Verification Futures Conference-“Challenges faced in Hardware Verification” on 4 Feb 2016.

You can view the slides and recordings here