The Formal Property Verification (FPV) methodology often gets used in the last step of verification flow, after much time spent building a complex random constrained UVM environment where some corner cases are still not covered.

Other times, FPV is used when a silicon bug is found that was not raised during the dynamic verification phase. This article examines a case of digital block verification using the formal property verification methodology versus the same block tested in UVM. Read More

Find out how T&VS Formal Verification techniques helps to improve the quality of Verification.