Dan Benua, principal corporate applications engineer with the Synopsys Verification Group, argues in this article that as SoC designs become more complex then we need to think about potential solutions offered by formal verification.

Dan identifies three solutions offered by formal:

  • Interconnect verification to ensure the large numbers of IP have been correctly connected
  • Sequential verification to ensure changes made for low power do not affect functionality
  • Automated clock domain crossing checks

These static formal techniques are cheaper and more comprehensive than the dynamic verification alternatives.

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