TVS has developed a SystemC library to enable UVM verification to be performed using SystemC rather than System Verilog. This is being used by BluWireless – see here . TVS will be at DVCon Silicon Valley during March 2nd to March 5th – visit our booth if you want to find out more.

You might also be interested in the European Project “VERDI” which provides Universal Verification Methodology (UVM) in SystemC to Accellera Systems Initiative as new industry standard proposal.