Nick Heaton and Avi Behar of Cadence correctly identify modern chips require the  interconnect to serve as the communication hub for various IP cores within the SoC. Verifying the functionality and performance of SoC interconnects can be a complex task, given the amount of masters and slave.

TVS also identified the significance of this challenge when it created the NoC  VIP.

Performance verification is obviously key and in this article Nick and Avi describe five important areas of focus for performance analysis.

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