In a recent blog for EDN, Karthik Nagappan (general manager of T&VS India) shared his perspective on DAC2014 and the latest developments in Verification. A short abstract of the article is enclosed below.
One of the many sessions at DAC this year was looking beyond functional verification to the challenges in non-mainline verification. This can take up to 30% of the total verification effort, so as the verification challenge grows, so do the non-mainstream elements, such as initialization and reset sequences, reliability, power management, built in self test (BIST) mechanisms, and debug and trace logic. Despite advances in automating formal functional verification using “apps” built into most formal verification tools, non-mainline verification is characterized by ad-hoc and manual methods, and the absence of methodologies, technologies, and tools.
Researchers from IBM in Germany and Israel, as well as Intel in Israel are looking closely at these challenges and how to verify and validate these elements. Researchers at Duke University in North Carolina are also looking at how dynamic power management designs can be architected to be formally verifiable.
So there are still plenty of challenges to keep me and my company busy, as an integral part of the semiconductor design industry. Bringing all these tools together in a coherent verification flow with the right coverage analysis is still a challenge for many companies right around the world, and the tools and expertise come from all over.