On 19th March, all roads lead to the Verification Futures Conference at Hotel Royal Orchid, Bangalore. With many Verification specialists and industry giants already confirming participation, this event is a must-attend for Verification professionals. What’s more, it is completely free!
Mr. Vikas Gautam, the Director of Corporate Application Engineering, Asia Pacific, Synopsys will open the proceedings. This will be followed by 3 exciting Challenge papers which will chart out the most common challenges faced in Verification closure today.
Dr. Mike Bartley, the CEO and founder of Test and Verification Solutions, will then recapture the challenges presented at the European Verification Futures Conference held in UK, France and Germany last November.
Also lined up are presentations by Mr. Jacek Majkowski from Aldec on Standard Co-Emulation Modeling Interface (SCE-MI), Mr. Naresh Ramachandran from Cadence on System and Soc Verification Trends and Mr. Mark Olen from Mentor Graphics on technology evolution in Functional Verification.
Broadcom will present a user paper that will focus on reducing chip level verification effort by optimizing gate level simulation and package-aware testbenches. For those aiming to develop a scalable verification framework, we have a presentation by NXP focusing on techniques to reduce verification turnaround times at module, sub-system and system levels.
Sounds exciting, huh? Wouldn’t you like some help to solve your Verification problems in one place? Register now!