Today, SoC designs use a large number of clock domains that run asynchronously to each other. Although the use of smaller individual clock domains helps to improve verification of subsystems apart from the context of the full SoC, the checks required to ensure that the full SoC meets its timing constraints have become increasingly time consuming.

Managing and verifying design constraints presents a number of challenges to methodology developers and verification engineers.  An article from Real Intent explores how to address constraints and exceptions management across full-chip SoC designs which allows designers to reduce design cycle times and improve the quality of the design constraints.

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