With increasing design complexities in power architecture and complex power domain partitioning, it is becoming imperative to drive functional and physical verification of these complex power logic hand in hand.Design and verification teams are struggling to keep up with two vectors – the ever increasing number of IP blocks and subsystems in modern SoCs & the growing use of software for power management. This article from Semiengineering describes how to handle and achieve low power coverage. Read More

Find out how T&VS low-power verification flow provides a seamless solution to verification challenges and allows for quick debugging of issues related to errors in the low-power design intent.