If you haven’t yet registered for the Verification Futures conference on 19th March, 2013 at Hotel Royal Orchid, Bangalore, do it now!
We have an exciting array of speakers from Broadcom, NXP, Aldec, Mentor Graphics, Synopsys, Cadence, Breker Systems and Doulos among others. They will be covering a wide range of topics encompassing the Verification spectrum.
Managers can benefit from Broadcom’s user paper on reducing chip level verification effort and NXP’s challenge paper on developing a scalable Verification environment. Breker systems will present on generation and visualization of multi-Threaded multi-core testcases.
For those interested in exploring trends in Verification, we have papers on Standard Co-emulation Modeling Interface (SCE-MI) and technology evolution in Functional Verification. Mr. John Aynsley from Doulos considers the feasibility of UVM adoption and explains how using SystemVerilog with UVM to create your test benches differs from using Verilog or VHDL. Test and Verification solutions will be presenting on ARM-based SoC verification.
If you are facing any challenges in Verification closure, this is the place to be! Register now for live participation.