Every survey on design and verification effort points to debug being our biggest time consumer. Over the past 20 years I have seen a number of game changes in verification: constrained random; functional coverage; assertions mutation. However, I have not seen any debug game changer but there is always continuous improvement.

So it is good to see that the Mentor Graphics is making a Questa_UVM  add-on SystemVerilog package which enables better UVM debug for Questa users.

See here for details