As the complexities of SoCs are increasing day by day, multiple clock sources are available in SoCs, which provide clocks of wide frequency ranges (varying from KHz range to MHz range). Moreover depending upon the power and functionality requirements, we can have different power modes, say full power modes and low power modes and ultra-low power modes in SoC.

Verification of all the clock sources is a tedious work, Further the complexity increases if we make a transition from one mode to another mode, say sweeping past across all modes and having different clock configurations in each mode.

In this article Siddharth Garg , Naveen Jakhar & Amit Bathla (all from Freescale Semiconductor) outline their approach to overcoming this.

Read more.