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Modeling and Verification of Mixed Signal IP using SystemVerilog

Mixed signal IP design and verification have become increasingly complex and compute-intensive. Modelling and verifying complete behavior of the IP provides both digital and analog designers the required confidence in design before proceeding into device level designs. This article presents a methodology to model and verify a mixed-signal IP using SystemVerilog.

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Find out how T&VS successfully verified the Mixed Signal IP Designs.

19th August, 2016|Blog, Thought Leadership|