Portable Stimulus Specification tends to bring applications where a given verification scenario needs to be reused across multiple verification engines, such as simulation, emulation, and post-silicon, or must be reused between block-level verification and SoC-level verification.

This article from Cadence define a stimulus specification standard that enables the definition of stimulus that is portable from block to system level verification, and portable across the verification engines such as, simulation, emulation, and FPGA prototype.

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Find out how T&VS portable stimulus specification addresses today industry verification challenges.