Wez Davey will highlight the key challenges in achieving predictable verification productivity in DisplayLink’s IC development process. Wez sees three key points to achieving this: getting even greater re-use of FPGA and simulation platforms within multiple discipline teams; spending less time fixing RTL and testbench bugs; and spending less time fixing bugs in third party tools, IP and VIP.

Verification Futures, held on February 5th in Reading and online, is a unique free one day conference, exhibition and industry networking event organised by TVS to discuss the challenges faced in hardware verification. The event gives the opportunity for end users to define their current and future verification challenges and collaborate with the vendors to create solutions.

Register here.