Dr Clare Dixon from the University of Liverpool to present keynote address at Formal Verification 2017 – sharing her experiences from the EPSRC-funded Trustworthy Robot Assistants project
June 1st 2017, Bristol, UK. – Test and Verification Solutions (T&VS) today announced details of the keynote presentation and the full program of technical presentations and panel discussion for Formal Verification 2017 (FV2017). Now in its Fifth successful year FV2017 is organised by T&VS and is Europe’s premier forum dedicated to discussing the application of Formal-based techniques to the verification and validation of complex SOCs, embedded hardware and software.
FV2017 is a one-day, free-to-attend conference that takes place in Reading, UK on Tuesday 27 June 2017. It is also available as a simulcast webinar.
“Once again, we have a very strong program and I’m especially pleased to have Dr Clare Dixon from the University of Liverpool join us to provide the keynote and to share her perspective on Robotic Assistants and what we need to do to ensure they are reliable, safe and trustworthy.” said Mike Bartley, CEO and Founder of T&VS. “Clare has over 20 years’ experience working in Formal and her award winner paper “The Fridge Door is Open” sets the scene for what we can expect.”
- Verification and Validation of Robotic Assistants
– Clare Dixon (Senior Lecturer), Department of Computer Science, University of Liverpool
- Formal Verification by the Book: ISA Formal at ARM
– Will Keen, Senior Engineer, CPU Group, ARM.
- A Modern Approach to Multi-Engine Metric Driven Verification
– Vincent Reynolds, Senior Product Engineer Formal R&D, Cadence.
- Exhaustively Verify SEU Mitigation Techniques Using Formal Verification
– Mark Handover, Applications Engineer, Mentor, A Siemens Business
- Open Source Tools for Formal Verification of Verilog HDL
– Clifford Wolf, Independent Researcher
- Coverage Reloaded: Signing Off Designs with Confidence
– Dr Ashish Darbari, Director, Product Management, OneSpin Solutions
- Porting and Verifying a pre-RTL Legacy Design
– Elchanan Rappaport, President, Gila Logic
- Formal for the Masses: The Latest and Greatest in User Friendly Formal Technology
– Iain Singleton, Formal Verification Specialist, Synopsys
- Are we there yet? Twenty years of formal verification in critical software …
– Rod Chapman, (Principal Engineer) Altran UK
For additional information and to register please visit:
FV2017 is free to attend and is made possible through the support of its sponsors: Cadence, Mentor, Onespin Solutions, Synopsys and T&VS.
T&VS (Test and Verification Solutions Ltd) provides services and products to organisations developing complex products in the microelectronics and embedded systems industries. Such organisations use T&VS to verify their hardware and software products, employ industry best practice and manage peaks in development and testing programmes. T&VS’ embedded software testing services includes onsite/offshore testing support including assistance with safety certification and security testing. T&VS hardware verification services include onsite/offshore verification support and training in advanced verification methodologies. T&VS also offers Verification IPs and its own Verification (EDA) signoff tool.
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