The performance of clock domain crossing (CDC) verification at SoC level relies on flat simulation runs. Due to increase in the number of clocks in larger, faster and more complex designs, the use of CDC verification has reduced. Flat CDC verifications are too intensive, time-consuming, and result in high noise. The dispersed design efforts require a distributed CDC verification mechanism where each module can be verified separately. This article discusses about how various hierarchical data models help to improve the performance of flat CDC verification on SoC.

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