Testbenches written in SystemVerilog and UVM face the problem of configurability and reusability between block- and system-level. Whereas reuse of UVCs from a block- to a system-level verification environment is relatively easy, the same cannot be said for the UVC’s connection to the harness.
The interfaces that these UVCs need changes from connections to primary inputs and outputs at block level to a set of hierarchical probes into the DUT at system level. This requires a re-write of all interface connections and hinders reuse. This article demonstrates how to write interface connections and use them in both block- and system-level testbenches.
Find how T&VS reusable verification framework solves the problem of configurability and reusability between block- and system-level.