This blog uses an example FFT design to demonstrate how to generate a bus-functional checker algorithm written in MATLAB, and it outlines how to integrate it into a UVM scoreboard.

HDL Verifier now has the ability to generate SystemVerilog DPI components from MATLAB and Simulink. With this capability, hardware verification teams can run the algorithmic models, system components, and test sequences used by their system design teams directly in their SystemVerilog simulator.

This not only saves the team the effort of reading the specifications and writing the tests and models, it also reduces the risk of misinterpreting the specifications. This is because the tests and models are essentially executable specifications generated directly from the MATLAB functions and the Simulink models.

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