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Reuse UVM RTL Verification tests for gate level simulation

Formal verification and random constrained tests based on UVM increase the probability to discover bug. During gate level simulation, RTL verification can’t be reused because the UVM Monitors are hooked on internal SoC signals that can change after the implementation phase.

This article from EDN describes how easy it is to create efficient self-checking tests that are reusable during gate level simulations.

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14th October, 2015|Blog, Thought Leadership|