After a very successful launch in 2014, we can now look forward to an even bigger and better DVCon Europe 2015 in Munich on November 11-12.
Sponsored by the Accellera Systems Initiative, DVCon is a long established event in the USA but now also runs in Europe and India, with DVCon Europe rapidly establishing itself as the major European Design and Verification conference. Definitely the place to be – to find out more visit the DVCon Europe 2015 website.
T&VS Participation at DVCon Europe
At this year’s event T&VS will be presenting a tutorial, participating in a panel, chairing the poster session, presenting a poster as well as exhibiting.
- Tutorial: Verifying Functional, Safety and Security Requirements (for Standards Compliance)
- Panel: The Functional Verification Roadmap: Where will we be in Five Years?
- Poster: A SystemC-based UVM Verification Infrastructure
- Exhibiting: Stand F2
If you’re visiting DVCon Europe please check out these two sessions and come along to our stand for the latest solution demos and announcements; including the latest updates to asureSIGN, our leading-edge leading Requirements Driven Verification tool – or simply stop by for a chat, it will be great to meet you.
|Title:||Verifying Functional, Safety and Security Requirements (for Standards Compliance)|
|When:||Date: Wednesday, November 11, 2015|
Time: 11:00 – 12:30
|Presenters||Mike Bartley, Test and Verification Solutions, United Kingdom.|
Dave Kelf, OneSpin Solutions, USA.
|Tutorial Abstract:||Markets such as automotive, avionics, nuclear, medical, rail, industrial, etc. require compliance to stringent development standards to ensure the devices are safe. As the devices become increasingly connected then security also becomes increasingly important. The standards require developers to minimise errors in such devices and to also ensure that the device can recover safely from any errors.Errors in such devices can come from two main sources: systematic design errors introduced during the development process; random physical errors occurring in the field. Both types of error need to be addressed – the former is addressed through mandating stringent development practices and the latter through error detection and correction mechanisms.The types of development practices mandated vary according to the safety integrity level assessed for the device but all safety levels mandate that requirements are properly captured and traced through development to verification.|
In this tutorial we consider how functional, safety and security requirements can be traced to verification tasks and then subsequently signed off. The tutorial will cover the following topics in detail:
|Title||The Functional Verification Roadmap: Where will we be in Five Years?|
|When:||Date: Wednesday, November 11, 2015|
Time: 15:30 – 17:00
|Overview||Engineers are confronted with a confusing array of functional verification options and emerging standards. This 90-minute tutorial panel will consider and predict various areas of advancements required in functional verification for the next five years. Issues to be discussed include the creation of an effective flow with tools from many sources, the collection and leverage of metrics to measure progress, the impact of safety-critical device verification, and increased software content. Experts in these different areas will consider questions, such as the effectiveness of existing standards, including UVM, SystemC and UCIS, and the likely evolutionary paths of verification flows.Join moderator (to be named) and distinguished verification leaders with European connections who will represent an accurate picture of what progress has been made and what is still missing in functional verification. They will attempt to sort out which standards are gaining momentum and recommend a sensible way to develop a functional verification strategy to manage today’s challenges. Audience participation in the debate is welcome.Each panelist will deliver a 5-7 minute technical talk, including practical examples and user experiences. After the presentations, panelists will interact with the audience to discuss and debate the presented material, challenges and address next-generation solutions. Recommendations for future developments are expected.|
|Panelists and Topics|
|Title||A SystemC-based UVM Verification Infrastructure|
|When:||Date: Thursday, November 12, 2015|
Time: 12:45 – 13:45
|Presenters||Mike Bartley and Harshavardhan Narla|
Test and Verification Solutions, United Kingdom.