Job Title:

Senior ASIC/FPGA Verification, System Verilog

Job Code:


Job Description

  • The project scope is to develop new radio technology in Radio Base Stations.
  • You will work with functional verification of new ASICs and FPGAs.
  • The work will be carried out in close cooperation with RTL designers.

Competence/Experience – Mandatory:

  • Long experience from ASIC/FPGA verification and test bench development
  • Excellent knowledge of System Verilog and UVM
  • Good programming skills (neat, commented, maintainable code, no warnings)
  • Excellent debugging skills of complex designs
  • Experience with IP level and system level verification
  • Proficient in verification planning, reporting and driving verification closure
  • Good skills in working with UNIX and/or Linux

Competence/Experience – Optional:

  • Experience from working with RTL and UPF simulations
  • Experience with Matlab, and signal processing
  • Experience with analog-mixed-signal type ASICs
  • Experience in Specman/e
  • Experience using formal properties and tools, such as Jasper, OneSpin, InFact and similar
  • Experience in using golden models/reference models in a test bench
  • C-programming
  • Experience in agile ways of working, in particular agile scrum
  • ClearCase version control system experience
  • VHDL knowledge
  • Scripting in Perl, Python, Bash or C-shell


  • 7+ Years


  • Sweden


  • Highly competitive to match experience and capability
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