Frustrated by all of the manual effort and time you’re spending developing complex system-level coverage-driven tests to verify your system on a chip (SoC)? Cadence Perspec™ System Verifier automates this entire process, reducing complex use-case scenario development from weeks to just days. Compared to manual test development, you’ll be able to generate 10X more tests using this platform

This EDN blog explains Cadence’s Perspec System Verifier which claims up to ten-time productivity improvement in system-on-chip verification by, among other strategies, automating some of the manual tasks when preparing system-level coverage-driven test development. It marks a shift towards software-driven verification, rather than (or, as well as) one that starts at the hardware logic level.

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