The Latest Design Verification Methodologies
Key Topics Covered
Attendees will be able to:
- Understand the process of Design Verification, its complexities and limitations
- Develop a verification plan, set verification goals and select verification levels (block, SoC), methods, techniques and tools to achieve these
- Understand and use state-of-the-art dynamic verification techniques and methods including constrained pseudo-random test generation, coverage collection and analysis, advanced checking, and assertion-based verification
- Be able to develop test benches and tests at SoC level, use appropriate metrics to measure what has been verified and use that data to make tape-out decisions
- Be able to follow a well-defined verification process and produce the various deliverables (plans, reports, etc.) required of that process. The TVS verification process will be used as an example process.
- 4 days divided into interactive lectures and hands-on lab exercises
- Lab exercises are arranged on each day. There is an exercise and a solution sheet for each lab. In addition, the starting point for each lab is pre-coded to include the solution from the previous lab. This ensures that all attendees start a new lab from a consolidated point. To ensure attendees achieve the learning outcomes for each lab the solutions will be discussed at the end of each lab.
- Lectures include small group sessions for hands-on interactive problem solving such as analysis of a specification, identification of features for a verification plan, development of a cross product coverage model, identification of design properties for assertion-based and formal verification, formalization of design properties, analysis and interpretation of formal verification results etc.
- No prior knowledge of verification is required
- Familiarity with the digital design process and basic understanding of SoC architecture is assumed
- Familiarity with the basic functionality of the EDA tools used in the labs is assumed. –
- Basic programming skills are helpful for the lab exercises, so is familiarity with Verilog or SystemVerilog.
The course is a combination of interactive sessions and Hands-on lab exercises.
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