T&VS recently hosted a DVClub Europe with 4 leading edge talks on UVM. The first speaker was Matteo Barbati, Senior Digital Verification Engineer at STMicroelectronics who considered UVM Register Map Dynamic Configuration. Matteo considered how to create a verification environment that dynamically changes behaviour according to the configuration registers. He looked at their 2 main current solutions: Custom code (e.g. generate an event at each write operation); and updates to the IP-Exact model with UVM specific code. Matteo highlighted the drawbacks of these approaches and then went into detail on his proposed approach which uses a new uvm_reg_field class which turns on triggers for the desired fields only enabling synchronisation of the verification environment with register updates (e.g. update scoreboard if it depends on the values in a register). Matteo demonstrated the work through a Serdes IP verification project. Matteo finished by identifying the drawbacks of his approach: the code size and performance (they introduce 9 extra variables and 4 extra events for each register field). And thus, future efforts will go into reducing the code size overhead.

The second speaker, Jacob Sander Andersen, discussed a tool they have developed for generating bus traffic patterns. This addresses the issues when the designer requests specific patterns on the bus but finds it difficult to clearly communicate that effectively to the verification engineer resulting in several meetings and iterations. Jacob has developed a Transaction Sequence Model, built around a producer-consumer paradigm that allows the designer to better communicate and for the verification engineer to then generate the desired traffic. Jacob plans to add functional coverage to close the loop.

The meeting finished with Uwe Simm of Cadencewho considered Common UVM Register Model Issues and Pitfalls and Mark Handover of Mentor, A Siemens Business, who gave an overview of their Advanced UVM Debug tooling.

The next DVClub Europe Meeting will consider Artificial Intelligence in Verification on Tuesday 16th April, 2019. Sign up here for the event (including online access).