Assertion-based verification has been an integral part of modern-day design verification. Concurrent SVA is a powerful assertion language that expresses the definition of properties in a concise set of notations and rules. This article explains how a relatively simple assertion can be written without SVA with the use of SystemVerilog tasks and provides examples that demonstrate how some of the SVA limitations can be overcome with the use of tasks, but yet maintain the spirit of SVA.

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