Making your products more Reliable, Safe and Secure

Verification is crucial for programmable SoC designs

SoC designs today encompass an increasing number of programmable units to meet flexibility, performance and cost constraints. The emerging platform based design paradigm poses enormous challenges to conceptualize, implement,  verify and program today's complex SoC designs. This article from Embedded Computing outlines why high performance Verification is crucial for programmable SoC designs. Read More Find out how T&VS Verification services [...]

2016-08-23T07:26:48+00:0023rd August, 2016|Blog, Thought Leadership|

RTL Signoff vs. Functional Signoff

With the growth in size and complexity of today's SoC designs, reuse of design IP, RTL and functional errors results in unpredictability in the design process, long verification cycles and functional failures. This article from Cadence describes how SoC teams are now able to increase overall productivity and address the challenges of RTL and functional [...]

2016-07-15T06:09:02+00:0015th July, 2016|Blog, Thought Leadership|

How to ensure the design of the SoC fulfils all functional safety requirements

Functional safety is becoming increasingly important in industrial and automotive applications, as is adherence to the relevant standards (IEC61508 and ISO26262 respectively. This article from New Electronics focuses on the practical issues of building a functional safety SoC from its various components. Read More Find out how T&VS Functional Safety Services helps you to improve [...]

2016-07-08T06:28:31+00:008th July, 2016|Blog, Thought Leadership|

Software driven Verification drives tight links between emulation and prototyping

The FPGA prototyping segment addresses mostly validation of smaller designs or a single IP while emulation is being used for large SoC designs. The FPGA prototyping being used mostly for SW development while emulation is being used for HW/SW verification and full system validation. Prototyping is great on speed but doesn't offer as much internal visibility [...]

2016-05-23T06:14:26+00:0023rd May, 2016|Blog, Thought Leadership|

Essential ingredients for developing VIPs

Developing verification IP is time-consuming and requires expert knowledge of the protocol. This article from Anysilicon describes the essential ingredients that need to be taken care of while developing a VIP. Read More Find out how T&VS VIPs help verification engineers access to the industry’s latest protocols, interfaces and memories required to verify their SoC [...]

2016-04-11T05:40:36+00:0011th April, 2016|Blog, Thought Leadership|

Debug becomes a bigger problem

Design and debug are expanding beyond being a purely functional problem into other areas such as performance, power and security. This article from Semiengineering captures the conversation between Cadence, Synopsys and Mentor Graphics on how debug solution maximizes performance, capacity and automation for the complete SoC design and verification cycle. Read More Learn more about T&VS Hardware Verification

2016-02-25T06:03:16+00:0025th February, 2016|Blog, Thought Leadership|

Hardware Emulation to debug embedded system software

Hardware emulation differentiates itself from other verification tools with its high performance – an increasingly important requirement driven by software requirements. It can complete the entire verification task for SoC designs within a practical timeframe and alleviate the runtime problems associated with an event-based simulation. This article from Embedded Computing describes how to debug hardware [...]

2016-02-24T06:50:54+00:0024th February, 2016|Blog, Thought Leadership|

Verification IP: Build or Buy?

Verification IP (VIP) provides verification engineers access to the industry's latest protocols, interfaces and memories required to verify their SoC designs. The licensing models for IPs & VIPs vary and many design houses are in a state to choose ‘Make vs Buy’ for verification. This article from AnySilicon describes why buying of Verification IP outweighs [...]

2016-02-16T06:54:47+00:0016th February, 2016|Blog, Thought Leadership|

Are chips getting more reliable?

Chip reliability is emerging as a key metric in the semiconductor industry, alongside of power, performance and cost, but it is also becoming harder to measure and increasingly difficult to achieve.  This article from Semiengineering captures the conversation between industry experts on how to increase reliability of the chip. Read More Learn more about T&VS [...]

2016-02-10T05:55:16+00:0010th February, 2016|Blog, Thought Leadership|

Using Agile Methods for Hardware

Agile development methodology is seen as a quick and highly suited approach for various kinds of environments.  This article from Semiengineering captures a conversation between industry experts on how hardware teams use agile methods in SoC designs. Read More Learn more about T&VS Agile methods for Hardware Development

2016-02-08T06:03:50+00:008th February, 2016|Blog, Thought Leadership|