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Design patterns in SystemVerilog OOP for UVM verification

SystemVerilog supports templates for generic code writing using parameterized classes. Design patterns are optimized, reusable solutions to commonly occurring programming problems. They are more than just class definitions or a package of routines. This article shows what are some of the design patterns in the code that make up the UVM base class library. Read [...]

A SystemC-based UVM Verification infrastructure

TVS recently completed a SystemC-based Universal Verification Methodology (UVM) project for Blu Wireless Technology, a UK-based company that develops silicon-proven mmWave wireless baseband IP for advanced WiGig applications. Blu Wireless follows a SystemC-based design flow. Following an initial specification period, it was quickly agreed that the best approach would be to deploy a SystemC test [...]