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The Many Flavors of Equivalence Checking: Part 2, How SLEC Brings Automated, Exhaustive Formal Analysis to ECO/Bug Fix Verification

Granted, if a lot of bugs are cropping up late in the project, customers are typically willing to rerun their entire UVM test bench regression suite to make sure the all the fixes and new ECOs are effective and don’t break anything else. This article outlines how to combine automated exhaustive formal analysis to ECO/bug fix verification.

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Find out how T&VS Verification services help to meet the challenging requirements with respect to performance, flexibility and verify today’s complex designs effectively.

6th September, 2019|Blog, Thought Leadership|