Professor Ashish Darbari, Leader of Advanced Verification Methodology Group at Imagination Technologies Limited,will keynote at at the third annual TVS Formal Verification conference on Thursday, 21 May.
Ashish will outline the ten most common myths encountered and share his views on them
- Validation and Verification (V&V) costs nearly 70% of the overall DV effort by most industry estimates. Predictability and quality of V&V are two key challenges facing most of the semi-conductor industry, further exacerbated by the ever decreasing time-to-market pressures enforced by OEMs. Better planning, requirements engineering, consistent reviews, and sign-off are all key enablers to address the V&V challenges. Key decisions made in the use (or not) of verification methods can make a big impact on all the key enablers and the overall predictability and quality.
- Formal techniques have been in use in industry for more than 25 years, however its use has been chequered by several myths that surround it. Its successful use in deriving maximum ROI is often gated by unnecessary myths about what it is and isn’t capable of. This has the negative impact on its adoption and as a consequence affects the overall V&V both in quality and predictability. In this talk I will outline the ten most common myths I’ve encountered and I’ll share my views on them.
Hear this great talk and 8 other speakers at the free one day Formal Verification conference held at Reading, UK on Thursday, 21 May and you have the option to attend in person or via remote access.
Attendees will gain from the event whether they are just trying to learn how to apply formal verification or expert users.
Places are limited and this event often sells out so we recommend early registration.
Speaker and registration details can be found here.