How to improve throughput for gate-level simulation

Gate-level simulation dates back to a simpler time when IC designs were well simple. Yet, despite its age and relatively slow speeds, gate-level simulation remains essential to meeting verification goals. This article shows how to improve the performance of gate-level simulation and achieve verification goals.

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2018-10-18T04:49:44+00:0018th October, 2018|Blog, Thought Leadership|