Overcoming Low Power Verification Challenges For Mixed-Signal SoC Designs

With increasing SoC complexity and advanced power-aware architectures, a robust low power verification methodology is important for signing off the design at different stages from RTL through netlist. This article discusses about how to use a low power methodology to combine static and dynamic verification.

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2018-10-24T12:49:07+00:0024th October, 2018|Blog, Thought Leadership|