In a recent blog for EETimes, Mike Bartley (founder and CEO of TVS) shared his perspective on the Risks and Rewards of Early Tapeout.
Early tapeout has one clear advantage. The fastest platform for running tests is the silicon itself. Even the best emulator or FPGA can only operate at a fraction of the speed of the final target, assuming that the SoC can be mapped.
By moving to silicon quickly, the verification and software development teams gain access to a platform that will allow them to run many more test vectors and, potentially, finished code that will tease out bugs that may lie hidden within an enormous state space. It also allows for real use cases to be executed.
The advantage of speed has to be balanced against the clear risks of an early tapeout strategy. The greatest risk is that the limited amount of verification performed before tapeout does not identify a bug that leads to the silicon being dead on arrival or so badly compromised that large portions of the device have to be left off limits.
A bug that disables one small device could be tolerated. But if it interferes with the cache-coherency protocol that links the major CPUs, the team will have waited close to three months for a device that will only yield partial insights while they wait for the next re-spin. Those additional months, for any high-volume product, will be far more costly than the mask set itself….