TVS advanced verification training uniquely combines advanced verification techniques with their application to realistic designs. Attendees get the learn advanced verification techniques and then apply them
- Derive a test plan for a serial IP and then extend a UVM test bench to implement the tests
- Write assertions for the IP and add them to the test bench or try to prove them using formal
- Verify the integration of the IP into a small SoC by writing integration tests and functional level C-based tests
The course is aimed at
- Design Verification engineers
- Design Verification Managers
- Design Engineers looking to cross-train to verification
- Companies trying to move to the latest verification techniques and strategies
A practical course delivered by verification experts that can be tailored to individual company requirements.
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