The verification skills gap continues to challenge companies both large and small. John Aynsley, CTO at training specialists Doulos, speaking at Verification Futures considers the choices being made regarding verification languages and methodology on the most complex SoC projects as well as how FPGA design teams are dealing with their increasing verification challenges.

Verification Futures, held on February 5th in Reading and online, is a unique free one day conference, exhibition and industry networking event organised by TVS to discuss the challenges faced in hardware verification. The event gives the opportunity for end users to define their current and future verification challenges and collaborate with the vendors to create solutions.

Register here.