T&VS is pleased to announce the development of a new “Event Stream Generator”.

Processors (CPU, GPU, DSP, etc.) are becoming more complex and require more verification. The current best practise in processor verification is instruction stream generation.

The T&VS instruction stream generator (asureISG) will have the following major features

  • Offline generation: the instructions are generated in advance of simulation for quicker generation speeds.
  • Sequence generation: sequences of instructions can push a design into the corners where the bugs lurk!
  • Multicore support: asureISG can be programmed to generation instructions for multiple cores allowing it to generate sequences of instruction streams for multiple cores. Those sequences can interlaced with defined synchronisation points for multicore verification.
  • Coverage support: coverage models can be built into the generation to help direct the generation.

asureISG is currently under development with T&VS key clients but we are open to more early adopter partners who want to influence the development.

Contact Mike Bartley for more information.