In this article Doug Amos discussed the verification of the most complex designs is performed using a standard verification methodology, probably System Verilog based UVM. Many verification teams have ramped up on UVM, but others have yet to take the plunge. Why is that? And how big is the “plunge”?
The article explains why UVM hasn’t been adopted by some companies already? Is it not as “Universal” as we expected or are there barriers to its adoption? If so, what might these barriers be and how can they be overcome?