Engineers can achieve a tremendous jump in verification productivity by tapping into VIP when architecting SoCs, implementing their blocks, and performing system integration. But to realize that productivity boost, engineers and tool managers need to carefully evaluate the VIP offering from the principal vendors to avoid the false economy that accompanies VIP of poor quality [...]
Success stories are what they are. The ones that catch your attention are backed up with user experience. So, two of the three ARM AMB verification IP examples that Cadence Design Systems has announced may merit your further investigation. They involve Hisilicon and CEVA. More information available here.
To help our customers evaluate the quality of the T&VS VIP solutions we are pleased to make the following unit-level code samples and documentation available as a VIP Evaluation Package. You can view the package features here. For more information, please visit the VIP page.
T&VS helped a leading smartphone manufacturer with the verification of its MPHY Anlaog IP. The scope of the activity was to model a MIPI MPHY analog IP using Verilog-AMS with real and to verify the model using a UVM-MS based testbench environment. For more information visit here.
T&VS releases one of the first C- PHY UVM VIP which has extensive constrained random stimuli generation capabilities, configurable monitors and checks to ensure protocol compliance to MIPI standard for C-PHY specification 1.0. Pre-defined coverage bins enable easier extension and coverage collection. The VIP has been verified for protocol compliance with asureSign-T&VS' in-house Requirements tracking tool. [...]
PRESS RELEASE Bristol, UK, 29 September 2014 – T&VS, a leader in software test and hardware verification solutions, today announced that is presenting and exhibiting at the inaugural Design & Verification Conference and Exhibition Europe (DVCon Europe) to be held in Munich on 14-15 October 2014 at the Hilton City hotel. The company will be [...]
PRESS RELEASE Bristol, UK, 23 September 2014 –T&VS, a leader in software test and hardware verification solutions, today announced that it has joined the MIPI Alliance, which develops interface specifications for mobile and mobile-influenced industries. The move reflects the demand for T&VS’ Verification IP, especially in the mobile application sector that is moving quickly and [...]
Test and Verification Solutions (T&VS) has announced that it has expanded its asureVIP™ library of verification IP to cover protocols in MIPI, Memories, Universal Serial IO and Communication as well as a bespoke VIP development service. The T&VS VIP offers many advantages to the user such as access to the source code, flexible licensing agreements [...]
Read about the white paper here
Below is the pdf related to USB OVM Verification IP. T&VS_USB_OVM_VIP_PB_MAT_1_0