SoC design traditionally has been an ad-hoc process, with implementation occurring at the register transfer level. This is where verification starts, and after the blocks have been verified, it becomes an iterative process of integration and verification that continues until the complete system has been assembled.
This blog outlines the solutions of two problems –
1. The constrained random methodology removed processors from the design because they were not fully controllable?
2. Simulation has stopped, meaning that verification is forced to migrate onto emulators for integration and even for some block-level verification?